1. Field of the Invention
The present invention relates to a power semiconductor device.
2. Background Art
A widely known example of a power transistor for handling high current is a vertical power MOSFET.
An on-resistance of the vertical power MOSFET largely depends on an electric resistance of a drift layer (conduction layer). The electric resistance of the drift layer changes according to a dopant concentration of the drift layer. To raise this dopant concentration, it is required to consider a breakdown voltage of a pn junction between the drift layer and a base layer. This is because the dopant concentration cannot be raised higher than a limiting concentration decided according to the breakdown voltage. In this way, a tradeoff relationship is present between the breakdown voltage and the on-resistance. There is a limit decided by materials of the device to realize both improvement in the breakdown voltage and suppression in the on-resistance.
As an example of a structure for solving this problem, there is known a super junction structure where n pillar layers and p pillar layers are buried in the drift layer. In the super junction structure, a pseudo undoped layer is formed by setting an impurity amount (charge amount) of each n pillar layer equal to that of each p pillar layer. Then, a current is applied via the heavily-doped n pillar layers, thereby realizing low on-resistance exceeding the material limitation while keeping the breakdown voltage high. To keep the high breakdown voltage, it is required to control the impurity amounts of the n pillar layers and the p pillar layers with high accuracy.
In a power semiconductor device where a MOSFET is formed on a drift layer of a super junction structure, the super junction structure is formed not only in a device part but also in a terminal part. However, in this case, there is a problem that it is difficult to set a breakdown voltage of the terminal part higher than that of the device part. In this case, if avalanche breakdown occurs, electric field locally concentrates on the terminal part, possibly resulting in breakdown of the terminal part.
JP-A 2004-134714 (KOKAI) discloses an example of a semiconductor device including parallel pn connection layers, each of which includes a p-type semiconductor region and an n-type semiconductor region, wherein an impurity concentration of a central portion of each semiconductor region is set higher than that of side portions of each semiconductor region. In a semiconductor region, the central portion is arranged apart from a junction plane between the semiconductor region and its adjacent semiconductor region, and the side portions are arranged closer to the junction plane.
Further, JP-A 2006-324432 (KOKAI) discloses an example of a semiconductor device including parallel pn connection layers, each of which includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, wherein an impurity concentration of the second conductivity type semiconductor layer is 1.15 times or more as high as that of the first conductivity type semiconductor layer.